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Serial
Port Control ( SCON ) Register
| MSB |
|
LSB |
SM0 |
SM1 |
SM2 |
REN |
TB8 |
RB8 |
TI |
RI |
Where SM0, SM1 specify the serial port mode, as follows
SM0 |
SM1 |
Mode |
Description |
Baud Rate |
0 |
0 |
0 |
Shif Register |
fosc/ 12 |
0 |
1 |
1 |
8 bit UART |
variable |
1 |
0 |
2 |
9 bit UART |
fosc/64 fosc/32 |
1 |
1 |
3 |
9 bit UART |
variable |
Note:
| SM2 |
Enables the multiprocessor communication
feature in Modes 2 and 3. In Mode 2 or 3, if SM2 is set to 1, then
Rl will not be activated if the received 9th data bit (RB8) is 0.
In Mode 1, if SM2=1 then RI will not be activated if a valid stop
bit was not received. In Mode 0, SM2 should be 0. |
| REN |
Enables serial reception. Set by software to
enable reception. Clear by software to disable reception. |
| TB8 |
The 9th data bit that will be transmitted in
Modes 2 and 3. Set or clear by software as desired. |
| RB8 |
In Modes 2 and 3, is the 9th data bit that
was received. In Mode 1, it SM2=0, RB8 is the stop bit that was
received. In Mode 0,
RB8 is not used. |
| TI |
Transmit interrupt flag. Set by hardware at
the end of the 8th bit time in Mode 0, or at the beginning of the
stop bit in the other modes, in any serial transmission. Must be
cleared by software. |
| RI |
Receive interrupt flag. Set by hardware at
the end of the 8th bit time in Mode 0, or halfway through the stop
bit time in the other modes, in any serial reception (except see
SM2). Must be cleared by software. |
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Programmer
ISP
89s
Free Software
a. Edsim 51
b. MIDE-51
c. ATMEL ISP
Lesson 1:
Architecture
1.1.Memory
1.2.SFR
1.3.Addressing
1.4.Instruction
Set
1.5.Assignment
Lesson 2:
Input Output
2.1.LED
2.2.Swicht
2.3.7
Segmen
2.4.LCD
Character
2.5.ADC
2.6.DAC
2.7.Motor
Stepper
2.8.Keypad
2.9.Assignment
Lesson 3:
Timer Counter
3.1.Basic
3.2.Mode
0
3.3.Mode
1
3.4.Mode
2
3.5.Mode
3
3.5.Assignment
Lesson 4:
Serial Comm.
4.1.Basic
4.2.LED
4.3.Rotate
LED
4.2 ADC
4.3.LCD
4.4.Assignment
Lesson 5:
Interuption
5.1.Basic
5.2.Timer
5.2.External
5.3.Assignment
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